In a nonvolatile semiconductor memory, such as a flash memory, it is known that a plurality of local bit lines is coupled to a common global bit line and each of the local bit lines is coupled to memory cells. Related arts are discussed in International Publication Pamphlet No. WO2002/082460, and Japanese Laid-open Patent Publication No. 2003-036203 and No. 2004-318941. In this type of semiconductor memory, a sense amplifier is coupled to the local bit line and the logic of data held in the memory cell is read without using a reference memory cell. For example, in a read operation, after precharging the local bit line, the voltage of the local bit line is changed by a cell current flowing through the memory cell to be accessed, and then data is read by detecting a change in the voltage using the sense amplifier. Related arts are discussed in Japanese Laid-open Patent Publication No. Hei10-275489 and No. 2001-160297.
Also, a nonvolatile semiconductor memory is known, wherein the activation timing of a sense amplifier in a read operation is varied according to an operation mode. A related art is discussed in Japanese Laid-open Patent Publication No. 2002-367390. A nonvolatile semiconductor memory is known, wherein in a read operation, the voltage of a reference bit line is changed by a current flowing through a reference memory cell and an activation timing of a sense amplifier is generated. A related art is discussed in Japanese Laid-open Patent Publication No. 2007-87512.
Moreover, a nonvolatile semiconductor memory is known, wherein a switch for coupling each of the bit lines to a ground line is provided and wherein an adjacent bit line of the bit line onto which data is read from a memory cell is coupled to the ground line via the switch. Related arts are discussed in Japanese Laid-open Patent Publication Nos. Hei9-293389, 2001-325797, and 2004-158111.
When the voltage of the bit line is changed by the cell current flowing through the memory cell and data is read, the activation timing of the sense amplifier needs to be set in accordance with the electric characteristic of the memory cell.